Reliability of integrated circuits is a significant consideration both in terms of fabrication and subsequent use. Attempts are continually being made to ensure high reliability at all stages of the fabrication process. For example, where feasible, Electro-Migration (EM) test structures are incorporated on semiconductor wafers with the formation of integrated circuits therein. Each integrated circuit can then individually be electrically bonded to the test structures to determine whether electro-migration may cause failure of the integrated circuit.
Today's metallization practice is to layer aluminum (Al) interconnects with thin films of refractory materials, such as titanium or tungsten, so that if a void in the aluminum forms, electrical continuity through the interconnect is maintained, albeit at increased resistance. Unfortunately, the increased resistance is typically insufficient to identify the failed interconnect conductor. This is because the additional resistance due to the aluminum void is often insufficient to distinguish the interconnect line from a normal resistance sampling after accounting for measurement variations.
One area of traditional concern is the electro-migration (EM) characteristics of metal (e.g., aluminum, aluminum alloys, copper, copper alloys and/or refractory metal) conductors in the integrated circuit. Because of the very small line widths required for present-day IC's, the current density in these conductors, including runners and contacts, is very high, often exceeding 1×105 amp/cm2 in normal device operation. Therefore, if the metal is inadvertently thinner (or narrower) in some portions of the ruiner than in others, the current density will be even higher than the intended value at those locations. Since the failure rate due to EM problems increases rapidly as the current density increases, such unintended thinning of the runners may lead to unacceptable reliability of the IC. Still other factors may affect the EM characteristics, such as the presence of impurities or precipitates in the metal that forms the runners, the grain size of the metal, and various other geometry limiting effects.
Electro-migration has long been identified as the major metal failure mechanism. It is one of the worst reliability concerns for VLSI circuits and manufacturing. The problem not only needs to be overcome during process development period in order to qualify the process, but it also persists through the life time of the chip. Voids are created inside of the metal conductors due to metal ion movement caused by high density of current flow. In short, electro-migration failure is caused by a positive divergence of the ionic flux leading to an accumulation of vacancies, forming voids in the metal. It appears that ions are moved “downstream” by the force of “electron wind”. Electro-migration and its related failures therefore can be categorized as a wear-out mechanism. In general the failure rate is proportional to current density and the surrounding temperature. EM problem becomes worse as the feature sizes both in width and thickness of metal wirings are further scaled. The current density for wires that lack sufficient cross-sectional area can easily exceed 1×105 amps/cm2. It has been observed that metal lines crossing over steep corners tend to be thinner than normal. These corner regions as well as via structures are the most common locations for EM to take place.
Methods to slow down the EM effect have been proposed, including: (1) adding copper (0.5-4%) into Al film, (2) adding Ti (0.1-0.5%) into the Al film, (3) using CVD tungsten metal studs (4) using diffusion batrier liners, etc. Acceleration EM tests carried out using high current, voltage and temperature stress can screen out defective chips in a relatively short period of time. Several methods have been proposed to teach how to conduct these EM tests. One method to measure EM effect is taught by U.S. Pat. No. 6,147,361, entitled “Poly-silicon Electro-migration Sensor Which Can Detect and Monitor Electro-migration in Composite Metal Lines on Integrated Circuit Structures with Improved Sensitivity”. The EM sensor described in this patent has a poly-silicon body, a monitored metal piece, and two electrodes. The electrodes are used to probe the connectivity of the EM sensor built by using an intrinsic poly-silicon element. A long metal that is placed on top of the sensor is stressed by a high voltage. When the EM mechanism occurs within the metal, the resulting local joule heating will cause the mobility of the senor to drastically increase. This is an indirect measurement of EM. It doesn't test metal with topology with corners and via contact regions.
A better way to test EM is to directly measure resistance of a test structure formed by metal wiring as described in the U.S. Pat. No. 5,264,377, entitled “Integrated Circuit Electro-migration Monitor”. A test structure is designed to measure wire resistance in terms of voltage drop after a period of high-voltage and high-temperature stress. Again, this test structure can detect EM failure only on the emulated wires. That is, the wire, made of one metal level, exhibits only a small artificial topology, which is far from reality.
An improved test structure is proposed in the U.S. Pat. No. 5,514,974, entitled “Test Device and Method for Signaling Metal Failure of Semiconductor Wafer”. As described, the metal interconnects under test contain a plurality of metal segments connected together with vias. The structure is closer to real life interconnects. The resistance of the test structure is compared to a control structure which is less prone to failure. If the resistance deviation between test and control structures exceeds a certain level, the part fails the test and is then rejected. This is a more direct measurement of EM.
However, all the EM testing methods proposed so far can only be done at wafer level and during a specific test mode. These test sites are bulky and usually are built along the kerf area adjacent to a chip, or inside a specially designed test chip. These testing methods were focused on process qualification and/or screening out bad chips during burn-in tests. Once the chips are diced and packaged, the capability of EM monitoring through out its life time doesn't exist. EM degradation doesn't stop after the chip is installed in a system and shipped to customers. One may desire, therefore, an on-chip EM sensor that would continue to monitor the EM degradation when the chip is in service. Such a sensor would be extremely useful for an expensive, sophisticated system to predict a chip's lifetime. Moreover, one may desire a system that can perform a self-healing process to cure damage done by EM.